1. Field of the Invention
This invention relates generally to integrated circuit random access memory (RAM) systems and, more particularly, to the interface buffer circuits which convert signals generated by circuits implemented using transistor-to-transistor logic (TTL) technology to signals compatible with circuits implemented in complementary metal oxides semiconductor (CMOS) technology. The CMOS technology is typically used to implement RAM and dynamic RAM (DRAM) memory arrays.
2. Description of the Related Art
The buffer circuits, which convert the signals generated by the data processing system apparatus implemented in TTL technology into signals compatible with the memory apparatus implemented in CMOS technology, are critical to successful operation of the system interface for the following reasons. The TTL buffer circuits provide the interface for all signals introduced into the memory component. A incorrect detection of a voltage (signal) level can result in a malfunction. One source of malfunction has, in the past, been the incorrect level detection resulting from variation in the power supply voltage. Similarly, noise on the supply and/or input signals can result in an incorrect interpretation of the logic level of the input signal. Being an interface, the speed with which the signals are converted from TTL-compatible to CMOS-compatible signals can provide a limitation in the system performance. In low power applications, the power dissipation, whether in a static mode or in a switching mode, can be a critical parameter. And finally, "ringing" in the input signal should be minimized in order to prevent oscillation of the internal signals.
In addition, when a large number of switching circuits and a full chip activation are required, more noise is generated than the buffer circuits disclosed by the related art are capable of handling. This is particularly true when a high noise margin is required for the input buffer circuit. Differential-type input buffer circuits provide the best noise margins, but have the disadvantage that these circuit require a higher die-area and result in a greater power dissipation than conventional buffer circuits.
A need has therefore been felt for a buffer circuit for providing an interface between the circuits implemented in TTL technology and circuits implemented in CMOS technology which have high noise margins, are relatively insensitive to power supply variations, operate at high speed, can be implemented on a relatively low die-area, do not require a stable reference level, and are relatively intolerant to ringing noise imposed on the input signals.